SH7619 Datasheet, PDF (376/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
Figure 13.2 shows a flowchart of this procedure.
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR, DMARS)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?*¹
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR and DAR
updated
*²
Bus mode,
*³
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
TE = 1
NMIF = 1
No
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer aborted
DEI interrupt request (when IE = 1)
NMIF = 1
No
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer end
Normal end
Notes: 1.
2.
3.
In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE and
DME bits are set to 1.
DREQ = level detection in burst mode (external request) or cycle-steal mode.
DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Figure 13.2 DMA Transfer Flowchart
Rev. 5.00 Mar. 15, 2007 Page 338 of 794
REJ09B0237-0500