SH7619 Datasheet, PDF (29/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Figure 19.5 Port E....................................................................................................................... 578
Section 20 User Break Controller (UBC)
Figure 20.1 Block Diagram of UBC........................................................................................... 584
Section 21 User Debugging Interface (H-UDI)
Figure 21.1 Block Diagram of H-UDI........................................................................................ 605
Figure 21.2 TAP Controller State Transitions ............................................................................ 616
Figure 21.3 H-UDI Data Transfer Timing.................................................................................. 618
Figure 21.4 H-UDI Reset............................................................................................................ 618
Section 22 Ethernet Physical Layer Transceiver (PHY)
Figure 22.1 The block Diagram around PHY Module................................................................ 622
Figure 22.2 Architectural Overview ........................................................................................... 624
Figure 22.3 How to Derive MDIO Signal from Core Signals .................................................... 625
Figure 22.4 MDIO Timing and Frame Structure (READ Cycle) ............................................... 626
Figure 22.5 MDIO Timing and Frame Structure (WRITE Cycle).............................................. 626
Figure 22.6 100Base-TX Data Path ............................................................................................ 638
Figure 22.7 Receive Data Path ................................................................................................... 641
Figure 22.8 Relationship between Received Data and Some MII Signals.................................. 643
Figure 22.9 Manchester Encoded Output ................................................................................... 645
Figure 22.10 Role of Each Bit Field (Example of Rising Waveform)
Slope is Controlled in Four Segments................................................................... 661
Figure 22.11 Example of Connection with a Pulse Transformer (RJ45) .................................... 663
Section 23 PHY Interface (PHY-IF)
Figure 23.1 Block Diagram of PHY-IF ...................................................................................... 668
Section 25 Electrical Characteristics
Figure 25.1 External Clock Input Timing................................................................................... 720
Figure 25.2 CKIO Clock Output Timing and CK_PHY Clock Input Timing ............................ 720
Figure 25.3 Oscillation Settling Timing after Power-On............................................................ 721
Figure 25.4 Oscillation Settling Timing after Standby Mode (By Reset)................................... 721
Figure 25.5 Oscillation Settling Timing after Standby Mode (By NMI or IRQ)........................ 721
Figure 25.6 PLL Synchronize Settling Timing By Reset or NMI .............................................. 722
Figure 25.7 Reset Input Timing.................................................................................................. 723
Figure 25.8 Interrupt Input Timing............................................................................................. 724
Figure 25.9 Pin Drive Timing in Standby Mode ........................................................................ 724
Figure 25.10 Basic Bus Timing: No Wait Cycle ........................................................................ 727
Figure 25.11 Basic Bus Timing: One Software Wait Cycle ....................................................... 728
Figure 25.12 Basic Bus Timing: One External Wait Cycle ........................................................ 729
Figure 25.13 Basic Bus Timing: One Software Wait Cycle,
External Wait Enabled (WM Bit = 0), No Idle Cycle............................................ 730
Rev. 5.00 Mar. 15, 2007 Page xxix of xxxviii