SH7619 Datasheet, PDF (92/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 3 Cache
Address Array: The V bit indicates whether or not the entry data is valid. When the V bit is 1,
data is valid; when 0, data is not valid. The U bit indicates whether or not the entry has been
written to in write-back mode. When the U bit is 1, the entry has been written to; when 0, it has
not. The tag address is composed of 22 bits (address bits 31 to 10) used for comparison during
cache searches.
In this LSI, the upper three bits of 32 address bits are used as shadow bits (see section 7, Bus State
Controller (BSC)), therefore, the upper three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset. The tag address is not initialized by a
power-on reset.
Data Array: Holds 16-byte instruction and data. Entries are registered in the cache in line units
(16 bytes). The data array is not initialized by a power-on reset.
LRU: With the 4-way set associative system, up to four instructions or data with the same entry
address can be registered in the cache. When an entry is registered, LRU shows which of the four
ways it is registered in. There are six LRU bits, controlled by hardware. The least-recently-used
(LRU) algorithm is used to select the way.
When a cache miss occurs, six LRU bits indicate the way to be replaced. If a bit pattern other than
those listed in table 3.1 is set in the LRU bits by software, the cache will not function correctly.
When changing the LRU bits by software, set one of the patterns listed in table 3.1.
The LRU bits are initialized to 000000 by a power-on reset.
Table 3.1 LRU and Way to be Replaced
LRU (Bits 5 to 0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
2
1
0
Rev. 5.00 Mar. 15, 2007 Page 54 of 794
REJ09B0237-0500