SH7619 Datasheet, PDF (527/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
Regarding Transmit and Receive Classification: The transmit sources and receive sources are
signals indicating the state; after being set, if the state changes, they are automatically cleared by
the SIOF.
When the DMA transfer is used, a DMA transfer request is pulled low (0 level) for one cycle at
the end of DMA transfer.
Processing when Errors Occur: On occurrence of each of the errors indicated as a status in
SISTR, the SIOF performs the following operations.
• Transmit FIFO underflow (TFUDF)
The immediately preceding transmit data is again transmitted.
• Transmit FIFO overflow (TFOVF)
The contents of the transmit FIFO are protected, and the write operation causing the overflow
is ignored.
• Receive FIFO overflow (RFOVF)
Data causing the overflow is discarded and lost.
• Receive FIFO underflow (RFUDF)
An undefined value is output on the bus.
• FS error (FSERR)
The internal counter is reset according to the FSYN signal in which an error occurs.
• Assign error (SAERR)
 If the same slot is assigned to both serial data and control data, the slot is assigned to serial
data.
 If the same slot is assigned to two control data items, data cannot be transferred correctly.
Rev. 5.00 Mar. 15, 2007 Page 489 of 794
REJ09B0237-0500