SH7619 Datasheet, PDF (303/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Section 12 Ethernet Controller Direct Memory Access
Controller (E-DMAC)
This LSI includes a direct memory access controller (E-DMAC) directly connected to the Ethernet
controller (EtherC). A large proportion of buffer management is controlled by the E-DMAC itself
using descriptors. This lightens the load on the CPU and enables efficient control of data transfer.
Figure 12.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive
buffers in memory.
12.1 Features
The E-DMAC has the following features:
• The load on the CPU is reduced by means of a descriptor management system
• Transmit/receive frame status information is indicated in descriptors
• Achieves efficient system bus utilization through the use of block transfer (16-byte units)
• Supports single-frame/multi-buffer operation
Transmit
descriptor
Receive
descriptor
Transmit
buffer
Receive
buffer
External memory
This LSI
Internal bus
E-DMAC
External bus
interface
Internal
bus
interface
Descriptor
information
Transmit
DMAC
Descriptor
information
Receive
DMAC
Transmit
FIFO
Receive
FIFO
EtherC
Figure 12.1 Configuration of E-DMAC, and Descriptors and Buffers
Rev. 5.00 Mar. 15, 2007 Page 265 of 794
REJ09B0237-0500