SH7619 Datasheet, PDF (533/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
The only sources of interrupts that should be enabled in SPI-mode transfer are transmit data
transfer request (TDREQ), transmit FIFO empty (TFEMP), receive-data transfer request
(RDREQ), receive-FIFO full (RFFUL), and receive-FIFO overflow (RFOVF). Enabled or
disabled states are selectable by the interrupt enable register (SIIER). Interrupts from other sources
must be disabled at all times.
For the DMA transfer requests, the enabled sources are transmit-data DMA transfer request
(TDMA) and receive-data DMA transfer request (RDMA). Enabled or disabled states are
selectable by the interrupt enable register (SIIER).
In SPI mode, the baud rate is set by SISCR.
Table 16.13 States of Transmit and Receive Operations in SPI Mode
TXE RXE TDMAE RDMAE SPI Transmit/Receive Operation
0
0
Don’t care Don’t care Transmission/reception is disabled
0
1
0
1
Half-Duplex Reception
The transmit FIFO does not operate and dummy data is
transmitted from the MOSI. Data received at the MISO is
stored in the receive FIFO and is transferred by using the
DMA.
Receive operation continues as long as RE bit = 1; the
receive-FIFO overflow (RFOVF) status is set after the
receive FIFO has become full and further receive data is
ignored.
1
0
0
0
Half-Duplex Transmission
The data in the transmit FIFO is transmitted from the
MOSI. The receive FIFO does not operate, and data on
the MISO is ignored. When the transmit FIFO becomes
empty, the transmit operation is completed.
1
0
Half-Duplex Transmission
The data which has been transferred by using the DMA
to the transmit FIFO is transmitted from the MOSI. The
receive FIFO does not operate and data on the MISO is
ignored. When the transmit FIFO becomes empty, the
transmit operation is completed.
Rev. 5.00 Mar. 15, 2007 Page 495 of 794
REJ09B0237-0500