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SH7619 Datasheet, PDF (401/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series | |||
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Section 14 Compare Match Timer (CMT)
Section 14 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The
CMT has a16-bit counter, and can generate interrupts at set intervals.
14.1 Features
CMT has the following features.
⢠Selection of four counter input clocks
Any of four internal clocks (PÏ/8, PÏ/32, PÏ/128, and PÏ/512) can be selected independently
for each channel.
⢠Interrupt request on compare match
⢠When not in use, CMT can be stopped by halting its clock supply to reduce power
consumption.
Figure 14.1 shows a block diagram of CMT.
CMI0
PÏ/32
PÏ/512
PÏ/8
PÏ/128
Control circuit
Clock selection
CMI1
PÏ/32
PÏ/512
PÏ/8
PÏ/128
Control circuit
Clock selection
Channel 0
Module bus
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
CMT
Compare match timer start register
Compare match timer control/status register
Compare match timer constant register
Compare match counter
Compare match interrupt
Channel 1
Bus
interface
Internal bus
Figure 14.1 Block Diagram of Compare Match Timer
Rev. 5.00 Mar. 15, 2007 Page 363 of 794
REJ09B0237-0500
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