SH7619 Datasheet, PDF (343/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(1) Countermeasure
This problem does not occur with all of the bits in EESR. The description applies to some bits but
not others. Table 12.1 shows whether the problem can occur with the individual bits and whether
the state of the individual interrupt source is reflected in the descriptor.
Table 12.1 EESR Bits for which This Problem can Occur and Reflection of Interrupt
Sources in the Descriptor
Bit Bit Name Status
Possibility Reflection in Interrupt
of Problem Descriptor Source
31

Reserved



30
TWB
Write-back complete
Yes

Transmit
29

Reserved



28

Reserved



27

Reserved



26
TABT Transmit abort detected
Yes
Reflected in Transmit
TD0 bit8
(TFS8)
25
RABT Receive abort detected
No
Reflected in Reception
RD0 bit8
(RFS8)
24
RFCOF Receive frame counter overflow Yes

Reception
23
ADE
Address error
No

Others
22
ECI
EtherC status register interrupt No

source
Others
21
TC
Frame transmission complete
Yes
Reflected in
TD0 bit31
(TACT)
Transmit
20
TDE
Transmit descriptor empty
No

Transmit
19
TFUF Transmit FIFO underflow
Yes

Transmit
18
FR
Frame received
No
Reflected in Reception
RD0 bit31
(RACT)
17
RDE
Receive descriptor empty
No

Reception
16
RFOF Receive FIFO overflow
Yes
Reflected in Reception
RD0 bit9
(RFS9)
Rev. 5.00 Mar. 15, 2007 Page 305 of 794
REJ09B0237-0500