SH7619 Datasheet, PDF (36/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Table 16.11
Table 16.12
Table 16.13
Transmit and Receive Reset ............................................................................. 487
SIOF Interrupt Sources ..................................................................................... 488
States of Transmit and Receive Operations in SPI Mode ................................. 495
Section 17 Host Interface (HIF)
Table 17.1 Pin Configuration.................................................................................................. 505
Table 17.2 HIF Operations ..................................................................................................... 506
Table 17.3 Memory Map ........................................................................................................ 521
Table 17.4 Consecutive Write Procedure to HIFRAM by External DMAC........................... 528
Table 17.5 Consecutive Read Procedure from HIFRAM by External DMAC....................... 529
Table 17.6 HIFDATA Register Alignment for Access by an External Device ...................... 531
Table 17.7 HIF Registers (other than HIFDATA) Alignment for Access
by an External Device........................................................................................... 531
Table 17.8 Input/Output Control for HIF Pins........................................................................ 533
Section 18 Pin Function Controller (PFC)
Table 18.1 List of Multiplexed Pins (Port A) ......................................................................... 535
Table 18.2 List of Multiplexed Pins (Port B).......................................................................... 535
Table 18.3 List of Multiplexed Pins (Port C).......................................................................... 537
Table 18.4 List of Multiplexed Pins (Port D) ......................................................................... 538
Table 18.5 List of Multiplexed Pins (Port E).......................................................................... 538
Table 18.6 Pin Functions in Each Operating Mode ................................................................ 540
Section 19 I/O Ports
Table 19.1 Port A Data Register H (PADRH) Read/Write Operation.................................... 570
Table 19.2 Port B Data Register L (PBDRL) Read/Write Operation ..................................... 572
Table 19.3 Port C Data Registers H and L (PCDRH and PCDRL) Read/Write Operation .... 575
Table 19.4 Port D Data Register L (PDDRL) Read/Write Operation..................................... 577
Table 19.5 Port E Data Registers H, L (PEDRH, PEDRL) Read/Write Operation ................ 580
Section 20 User Break Controller (UBC)
Table 20.1 Data Access Cycle Addresses and Operand Size Comparison Conditions........... 597
Section 21 User Debugging Interface (H-UDI)
Table 21.1 Pin Configuration.................................................................................................. 606
Table 21.2 H-UDI Commands................................................................................................ 608
Table 21.3 External pins and Boundary Scan Register Bits ................................................... 609
Table 21.4 Reset Configuration .............................................................................................. 617
Section 22 Ethernet Physical Layer Transceiver (PHY)
Table 22.1 Pin Configuration.................................................................................................. 623
Table 22.2 4B/5B Code Table ................................................................................................ 639
Rev. 5.00 Mar. 15, 2007 Page xxxvi of xxxviii