SH7619 Datasheet, PDF (409/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 14 Compare Match Timer (CMT)
14.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing
has priority over the count-up. In this case, the count-up is not performed. The byte data on
another side, which is not written to, is also not counted and the previous contents remain.
Figure 14.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT
in bytes.
Peripheral operating
clock (Pφ)
Address
CMCSR write cycle
T1
T2
CMCNTH
Internal write
CMCNT count-up
enable
CMCNTH
N
M
CMCNTL
X
X
Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT
14.5.4 Conflict between Write Processes to CMCNT with the Counting Stopped and
CMCOR
Writing the same value to CMCNT with the counting stopped and CMCOR is prohibited. If
written, the CMF flag in CMCSR is set to 1 and CMCNT is cleared to H'0000.
Rev. 5.00 Mar. 15, 2007 Page 371 of 794
REJ09B0237-0500