SH7619 Datasheet, PDF (219/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
CKIO
A25 to A0
A11*
CSn
RAS
CAS
RD/WR
DQMxx
D
BS
Tp
Tpw
Tr
Tc1
Note: * Address pin to be connected to pin A10 of SDRAM.
Figure 7.24 Single Write Timing (Bank Active, Different Row Addresses)
Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Auto-
refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in
SDCR. A consecutive refreshing can be performed by setting bits RRC2 to RRC0 in RTCSR. If
synchronous DRAM is not accessed for a long period, self-refreshing mode, in which the power
consumption for data retention is low, can be activated by setting both the RMODE bit and the
RFSH bit to 1.
1. Auto-refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to
CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR
should be set so as to satisfy the given refresh interval for the synchronous DRAM used. First
make the settings for RTCOR, RTCNT, and the RMODE, then make the CKS[2:0] and
RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up
from the value at that time. The RTCNT value is constantly compared with the RTCOR value,
and if the two values are the same, a refresh request is generated and an auto-refreshing is
performed for the number of times specified by the RRC[2:0]. At the same time, RTCNT is
cleared to 0 and the count-up is restarted.
Rev. 5.00 Mar. 15, 2007 Page 181 of 794
REJ09B0237-0500