SH7619 Datasheet, PDF (539/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
No.
Time Chart
Start
1
Make settings for DMA.
SIOF/DMA Setting
Complete setting for DMA before making settings
for the SIOF.
SIOF/DMA Operation
2 Set SISCR, SIFCTR, SPICR, and SIIER.
Set the serial clock, threshold values for FIFO,
and RDMAE = 1
[Note] In SPI mode, registers SIMDR, SITDAR, SIRDAR,
and SICDAR should be set to their initial values.
3
Set the SCKE bit in SICTR to 1.
4
Set the FSE bit in SICTR to 1.
Set the RXE bit in SICTR to 1.
Start baud rate generator operation.
Initialize the frame in the SIOF (ie, initialize the
state of signal SS0), and enable reception.
[Note] Serial clock will not be output form the pin until
communication is actually started.
[Note] Communication is actually started after RXE = 1
has been set.
5
RDREQ=1?
No
Yes
6
DMA transfer
(Read from the SIRDR register.)
Read data from the SIRDR register.
7
Synchronously to SS0, receive data
from MISO.
No
8
Transfer complete?
Yes
9
Clear the RXE bit in SICTR to 0.
Executes reception.
At the point when a DEI interrupt is generated,
reception has already proceeded excessively.
Therefore, read the necessary amount of data from
FIFO and skip the remainder, or cancel by RxRST.
When the DMA transfr end interrupt is used, clear the IE
bit in DMA.CHCRn before the execution returns from the
interrupt service routine.
Disable reception.
Reception ends.
10
Clear the FSE bit in SICTR to 0.
To be prepared for the transmission/reception that
is resumed later, set FSE = 0 to synchronize
the frame in this LSI.
Set BPRS = 00000 and BRDV = 111
in the SISCR register.
11
Apply a pulse to bit RxRST in the
SICTR register (0->1->0 input).
To be prepared for the transmission/reception that
is resumed later, initialize inside the baud rate
generator.
Set the SISCR register to set
the baud rate again.
12
Change
No
communication mode?
If communication is not to be resumed
(branching to No), no further setting is needed.
To return to the same communication mode,
Yes
End go back to setting of FSE at step 4 of this flowchart.
13
With FSE=0, TXE=0, and RXE=0
held, start setting other bits.
Go on to 'Start' of the corresponding flowchart.
Figure 16.27 SPI Reception Operation (Example of Half-Duplex Reception by DMA with
RDMAE = 1)
Rev. 5.00 Mar. 15, 2007 Page 501 of 794
REJ09B0237-0500