SH7619 Datasheet, PDF (677/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
Table 22.2 4B/5B Code Table
CODE
RECEIVER
GROUP SYM INTERPRETATION (CO_MII_RXD)
TRANSMITTER
INTERPRETATION
(CO_MII_TXD)
11110 0
0 0000
DATA 0
01001 1
1 0001
DATA 1
10100 2
2 0010
DATA 2
10101 3
3 0011
DATA 3
01010 4
4 0100
DATA 4
01011 5
5 0101
DATA 5
01110 6
6 0110
DATA 6
01111 7
7 0111
DATA 7
10010 8
8 1000
DATA 8
10011 9
9 1001
DATA 9
10110 A
A 1010
DATA A
10111 B
B 1011
DATA B
11010 C
C 1100
DATA C
11011 D
D 1101
DATA D
11100 E
E 1110
DATA E
11101 F
F 1111
DATA F
11111 I
IDLE
Sent after /T/R/ until CO_TX_EN
11000 J
First nibble of SSD, translated to "0101"
following IDLE, else CO_RX_ER
Sent for rising CO_TX_EN
10001 K
Second nibble of SSD, translated to "0101" Sent for rising CO_TX_EN
following J, else CO_RX_ER
01101 T
First nibble of ESD, causes de-assertion of
CRS if followed by /R/, else assertion of
CO_RX_ER
Sent for falling CO_TX_EN
00111 R
Second nibble of ESD, causes deassertion of Sent for falling CO_TX_EN
CRS if following /T/, else assertion of
CO_RX_ER
00100 H
Transmit Error Symbol
Sent for rising CO_TX_ER
00110 V
INVALID, CO_RX_ER if during CO_RX_DV INVALID
11001 V
INVALID, CO_RX_ER if during CO_RX_DV INVALID
00000 V
INVALID, CO_RX_ER if during CO_RX_DV INVALID
Rev. 5.00 Mar. 15, 2007 Page 639 of 794
REJ09B0237-0500