SH7619 Datasheet, PDF (25/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 10 Power-Down Modes
Figure 10.1 Canceling Standby Mode with STBY Bit in STBCR.............................................. 232
Section 11 Ethernet Controller (EtherC)
Figure 11.1 Configuration of EtherC.......................................................................................... 234
Figure 11.2 EtherC Transmitter State Transitions ...................................................................... 254
Figure 11.3 EtherC Receiver State Transmissions...................................................................... 255
Figure 11.4 (1) MII Frame Transmit Timing (Normal Transmission)........................................ 256
Figure 11.4 (2) MII Frame Transmit Timing (Collision)............................................................ 256
Figure 11.4 (3) MII Frame Transmit Timing (Transmit Error)................................................... 257
Figure 11.4 (4) MII Frame Receive Timing (Normal Reception)............................................... 257
Figure 11.4 (5) MII Frame Receive Timing (Reception Error (1))............................................. 257
Figure 11.4 (6) MII Fame Receive Timing (Reception Error (2)) .............................................. 257
Figure 11.5 MII Management Frame Format ............................................................................. 258
Figure 11.6 (1) 1-Bit Data Write Flowchart ............................................................................... 259
Figure 11.6 (2) Bus Release Flowchart (TA in Read in Figure 11.5) ......................................... 260
Figure 11.6 (3) 1-Bit Data Read Flowchart ................................................................................ 260
Figure 11.6 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 11.5)................ 261
Figure 11.7 Changing IPG and Transmission Efficiency ........................................................... 262
Figure 11.8 Example of Connection to DP83846AVHG............................................................ 263
Section 12 Ethernet Controller Direct Memory Access Controller
(E-DMAC)
Figure 12.1 Configuration of E-DMAC, and Descriptors and Buffers....................................... 265
Figure 12.2 Relationship between Transmit Descriptor and Transmit Buffer ............................ 290
Figure 12.3 Relationship between Receive Descriptor and Receive Buffer ............................... 294
Figure 12.4 Sample Transmission Flowchart ............................................................................. 299
Figure 12.5 Sample Reception Flowchart................................................................................... 301
Figure 12.6 E-DMAC Operation after Transmit Error ............................................................... 302
Figure 12.7 E-DMAC Operation after Receive Error................................................................. 303
Figure 12.8 Timing of the Case where Setting of the Interrupt Source Bit in EESR
by the E-DMAC Fails ............................................................................................ 304
Figure 12.9 Countermeasure by Monitoring the Transmit Descriptor in Processing of
Interrupts Other than the Frame Transmit Complete (TC) Interrupt...................... 310
Figure 12.10 Method of Adding Timeout Processing................................................................. 312
Figure 12.11 Operation when E-DMAC Stops and the Transmit FIFO ..................................... 314
Figure 12.12 Processing Transmission without Handling of the TC Interrupt ........................... 317
Figure 12.13 Countermeasure for the Case with TC Interrupt-Driven Software: Addition of
Timeout Processing within the Limit Imposed by the Maximum Specified Time. 320
Rev. 5.00 Mar. 15, 2007 Page xxv of xxxviii