SH7619 Datasheet, PDF (239/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 8 Clock Pulse Generator (CPG)
Section 8 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock
(Pφ), a bus clock (Bφ), and a clock (Mφ) for the on-chip IEEE802.3-PHY (physical layer device,
hereinafter called PHY). The CPG consists of an oscillator, PLL circuits, and divider circuits.
8.1 Features
• Four clock modes
Selection of four clock modes depending on the frequency of a clock source and whether a
crystal resonator or external clock input is in use.
• Four clocks generated independently
An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip
peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface; and a clock (Mφ)
for the on-chip PHY.
• Frequency change function
Frequencies of the internal clock, peripheral clock, and clock for the PHY can be changed
independently using the PLL circuit and divider circuit within the CPG. Frequencies are
changed by software using the frequency control register (FRQCR) and PHY clock frequency
control register (MCLKCR) settings.
• Power-down mode control
The clock can be stopped in sleep mode and software standby mode and specific modules can
be stopped using the module standby function.
Rev. 5.00 Mar. 15, 2007 Page 201 of 794
REJ09B0237-0500