SH7619 Datasheet, PDF (267/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 10 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
0
MSTP19 0
R/W Module Stop Bit 19
When this bit is set to 1, the supply of the clock to the
EtherC and E-DMAC is halted.
0: EtherC and E-DMAC operate
1: Clock supply to EtherC and E-DMAC halted
10.4 Sleep Mode
10.4.1 Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral
modules continue to operate in sleep mode and the clock continues to be output to the CKIO pin.
10.4.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt other than a user break (NMI, H-UDI, IRQ, and on-chip
peripheral module) or a reset.
Canceling with Interrupt: When a user-break, NMI, H-UDI, IRQ, or on-chip peripheral module
interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the
priority level of an IRQ or on-chip peripheral module interrupt is lower than the interrupt mask
level set in the status register (SR) of the CPU, an interrupt request is not accepted preventing
sleep mode from being canceled.
Canceling with Reset: Sleep mode is canceled by a power-on reset or an H-UDI reset.
Rev. 5.00 Mar. 15, 2007 Page 229 of 794
REJ09B0237-0500