SH7619 Datasheet, PDF (159/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10
BSZ1
1*
R/W Data Bus Size
9
BSZ0
1*
R/W Specify the data bus width of each area.
00: Reserved (setting prohibited)
01: 8 bits
10: 16 bits
11: 32 bits
Notes: 1. The data bus width for area 0 is specified by
the external pin. These bits are ignored.
2. When area 5 or 6 is specified as PCMCIA
space, the bus width can be specified as
either 8 bits or 16 bits.
3. If area 3 is specified as SDRAM space, the
bus width cannot be specified as 8 bits.
4. These bits must be specified to either 01 or 11
before accessing to memory in other than
area 0.
8 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * CS0BCR fetches the external pin state (MD3) that specify the bus width at a power-on
reset.
Rev. 5.00 Mar. 15, 2007 Page 121 of 794
REJ09B0237-0500