SH7619 Datasheet, PDF (240/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 8 Clock Pulse Generator (CPG)
A block diagram of the CPG is shown in figure 8.1.
Oscillator unit
CKIO
XTAL
EXTAL
MD2
MD1
MD0
PLL circuit 1
(×1, ×2)
Crystal oscillator
PLL circuit 2
(×2, ×4)
Divider 2
×1
×1/2
×1/4
×1/5
Divider 1
×1
×1/2
×1/4
PHY clock
(Mφ)
Internal clock
(Iφ)
Bus clock
(Bφ = CKIO)
Peripheral clock
(Pφ)
Clock frequency
control circuit
CPG control unit
Standby control circuit
FRQCR
MCLKCR STBCR STBCR2 STBCR3 STBCR4
Bus interface
[Legend]
FRQCR: Frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
STBCR3: Standby control register 3
STBCR4: Standby control register 4
MCLKCR: PHY clock frequency control register
Internal bus
Figure 8.1 Block Diagram of CPG
Rev. 5.00 Mar. 15, 2007 Page 202 of 794
REJ09B0237-0500