SH7619 Datasheet, PDF (26/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
Figure 13.1 Block Diagram of DMAC ....................................................................................... 324
Figure 13.2 DMA Transfer Flowchart........................................................................................ 338
Figure 13.3 Round-Robin Mode................................................................................................. 342
Figure 13.4 Changes in Channel Priority in Round-Robin Mode............................................... 343
Figure 13.5 Data Flow of Dual Address Mode........................................................................... 345
Figure 13.6 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory) ............................... 346
Figure 13.7 Data Flow in Single Address Mode......................................................................... 347
Figure 13.8 Example of DMA Transfer Timing in Single Address Mode ................................. 348
Figure 13.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)........................................................ 349
Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)..................................................... 350
Figure 13.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)..................................................... 350
Figure 13.12 Bus State when Multiple Channels are Operating................................................. 352
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 353
Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 353
Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 354
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 354
Figure 13.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection ................ 355
Figure 13.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)............................. 356
Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
When DACK is Divided to 4 by Idle Cycles ........................................................ 358
Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
When DACK is Divided to 2 by Idle Cycles........................................................ 359
Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
When DACK is Divided to 4 by Idle Cycles ........................................................ 359
Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
When DACK is Divided to 2 by Idle Cycles ........................................................ 360
Section 14 Compare Match Timer (CMT)
Figure 14.1 Block Diagram of Compare Match Timer............................................................... 363
Figure 14.2 Counter Operation ................................................................................................... 367
Figure 14.3 Count Timing .......................................................................................................... 367
Figure 14.4 Timing of CMF Setting ........................................................................................... 368
Figure 14.5 Conflict between Write and Compare-Match Processes of CMCNT...................... 369
Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT...................... 370
Rev. 5.00 Mar. 15, 2007 Page xxvi of xxxviii