SH7619 Datasheet, PDF (140/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 6 Interrupt Controller (INTC)
6.6 Interrupt Operation
6.6.1 Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt from interrupt requests sent,
according to the priority levels set in interrupt priority level setting registers A to G (IPRA to
IPRG). Interrupts that have lower-priority than that of the selected interrupt are ignored*. If
interrupts that have the same priority level or interrupts within a same module occur
simultaneously, the interrupt with the highest priority is selected according to the priority
shown in table 6.2.
3. The interrupt controller compares the priority level of the selected interrupt request with the
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the
selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If
the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt
controller accepts the request and sends an interrupt request signal to the CPU.
4. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of
an instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception handling (see figure 6.5).
5. SR and PC are saved onto the stack.
6. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR.
7. The CPU reads the start address of the exception handling routine from the exception vector
table for the accepted interrupt, branches to that address, and starts executing the program.
This branch is not a delayed branch.
Note: * Interrupt requests that are designated as edge-detect type are held pending until the
interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing
the IRQ status register (IRQSR). Interrupts held pending due to edge detection are
cleared by a power-on reset or an H-UDI reset.
Rev. 5.00 Mar. 15, 2007 Page 102 of 794
REJ09B0237-0500