SH7619 Datasheet, PDF (536/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
Procedures for Transmission/Reception: Shown in figures 16.24 to 16.27 are examples of
settings for SPI transmission/reception along with the corresponding operations.
No.
Time chart
Start
1
Set SISCR, SIFCTR, and SPICR.
SIOF Setting
SIOF Operation
Set the serial clock and threshold values for FIFO.
[Note] In SPI mode, registers SIMDR, SITDAR, SIRDAR,
and SICDAR should be set to their initial values.
2
Set the SCKE bit in SICTR to 1.
3
Set the FSE bit in SICTR to 1.
Set the TXE and RXE bits in SICTR to 1.*
Start baud rate generator operation.
[Note] Serial clock will not be output form the pin until
communication is actually started.
Initialize the frame in the SIOF (ie, initialize the state
of signal SS0), and enable transmission and
reception.
[Note] Communication is actually started after SITDR
has been written.
4
TDREQ=1?
No
Yes
5
Set the SITDR register.
6
Synchronously to SS0, output the contents of
SITDR from MOSI and receive data from MISO.
7
No
RDREQ=1?
Yes
Set the data for transmission.
Executes transmission and reception simultaneously.
(Even when transmission is not necessary, dummy
transmission must be performed. The output of dummy
transmission can be masked by setting the pin function.)
8
Read the SIRDR register.
Read the received data.
Check SISTR.TFEMP (transmit FIFO empty) and
9
Transfer complete?
No
ensure completion of communication by using a wait
loop or other means. (Checking SISTR.TFEMP is
enough to confirm the completion of simultaneous
Yes
transmission and reception.)
10
Clear the TXE and RXE bits
in SICTR to 0.
Disable transmission and reception.
Transmission/reception end.
11
Clear the FSE bit in SICTR to 0.
To be prepared for the transmission/reception that
is resumed later, set FSE = 0 to synchronize
the frame in this LSI.
Set BPRS = 00000 and BRDV = 111
in the SISCR register.
12 Apply a pulse to bits TxRST and RxRST
in the SICTR register (0->1->0 input).
To be prepared for the transmission/reception that
is resumed later, initialize inside the baud rate
generator.
Set the SISCR register to set
the baud rate again.
13
Change
communication mode?
No
If communication is not to be resumed
(branching to No), no further setting is needed.
To return to the same communication mode,
Yes
End go back to setting of FSE at step 3 of this flowchart.
14
With FSE=0, TXE=0, and RXE=0
held, start setting other bits.
Go on to 'Start' of the corresponding flowchart.
Note: * For the case when interrupt generation on transmit FIFO underflow is enabled, set the TXE bit to 1 after setting data for transmission at step No.5.
Figure 16.24 SPI Transmission/Reception Operation (Example of Full-Duplex
Transmission/Reception by the CPU with TDMAE = 0)
Rev. 5.00 Mar. 15, 2007 Page 498 of 794
REJ09B0237-0500