SH7619 Datasheet, PDF (149/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Abbreviation I/O Function
WE0(BE0)
Output Indicates that D7 to D0 are being written to.
RAS
CAS
Connected to the byte select signal when a byte-selection SRAM is in
use.
Output Connected to RAS pin when SDRAM is in use.
Output Connected to CAS pin when SDRAM is in use.
CKE
IOIS16
Output Connected to CKE pin when SDRAM is in use.
Input PCMCIA 16-bit I/O Signal
Enabled only in little endian mode.
Drive this signal low in big endian mode.
DQMUU,
DQMUL,
DQMLU,
DQMLL
Output Connected to the DQMxx pin when SDRAM is in use.
DQMUU: Select signal for D31 to D24
DQMUL: Select signal for D23 to D16
DQMLU: Select signal for D15 to D8
DQMLL: Select signal for D7 to D0
WAIT
Input External wait input
MD5, MD3
Input MD5: Selects data alignment (big endian or little endian)
MD3: Specifies area 0 bus width (8/16 bits)
Note: * As pins A25 to A16 act as general I/O ports immediately after a power-on reset, pull-up
or pull-down these pins outside the LSI as needed.
7.3 Area Overview
7.3.1 Area Division
The architecture of this LSI has 32-bit address space. The upper three address bits divide the space
into areas P0 to P4, and the cache access methods can be specified for each area. For details, see
section 3, Cache. Each area indicated by the remaining 29 bits is divided into ten areas (five areas
are reserved) when address map 1 is selected or eight areas (three areas are reserved) when address
map 2 is selected. The address map is selected by the MAP bit in CMNCR. The BSC controls the
areas indicated by the 29 bits.
As listed in tables 7.2 and 7.3, memory can be connected directly to five physical areas of this
LSI, and the chip select signals (CS0, CS3, CS4, CS5B, and CS6B) are output for each area. CS0
is asserted during area 0 access.
Rev. 5.00 Mar. 15, 2007 Page 111 of 794
REJ09B0237-0500