SH7619 Datasheet, PDF (148/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
7.2 Input/Output Pins
table 7.1 lists the pin configuration of the BSC.
Table 7.1 Pin Configuration
Abbreviation I/O Function
A25 to A0
Output Address Bus*
D31 to D0
BS
I/O Data Bus
Output Bus Cycle Start
Asserted when a normal space, burst ROM (clock synchronous
/asynchronous), or PCMCIA is accessed. Asserted at the same timing
as CAS assertion in SDRAM access.
CS0, CS3, CS4 Output Chip Select
CS5B/CE1A Output Chip Select
CE2A
CS6B/CE1B
Chip enable for PCMCIA allocated to area 5 when PCMCIA is in use
Output Chip enable for PCMCIA allocated to area 5 when PCMCIA is in use
Output Chip Select
Chip enable for PCMCIA allocated to area 6 when PCMCIA is in use
CE2B
RD/WR
RD
Output Chip enable for PCMCIA allocated to area 6 when PCMCIA is in use
Output Read/Write
Connects to WE pins when SDRAM or byte-selection SRAM is used.
Output Read Pulse Signal (read data output enable signal)
Strobe signal to indicate a memory read cycle when PCMCIA is in use.
ICIOWR
ICIORD
WE3(BE3)
Output Strobe signal to indicate I/O write when PCMCIA is in use.
Output Strobe signal to indicate I/O read when PCMCIA is in use.
Output Indicates that D31 to D24 are being written to.
WE2(BE2)
Connected to the byte select signal when byte-selection SRAM is in use.
Output Indicates that D23 to D16 are being written to.
Connected to the byte select signal when byte-selection SRAM is in use.
WE1(BE1)/WE Output Indicates that D15 to D8 are being written to.
Connected to the byte select signal when byte-selection SRAM is in use.
Strove signal to indicate a memory write cycle when PCMCIA is in use.
Rev. 5.00 Mar. 15, 2007 Page 110 of 794
REJ09B0237-0500