SH7619 Datasheet, PDF (304/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.2 Register Descriptions
The E-DMAC has the following registers. For addresses and access sizes of these registers, see
section 24, List of Registers.
• E-DMAC mode register (EDMR)
• E-DMAC transmit request register (EDTRR)
• E-DMAC receive request register (EDRRR)
• Transmit descriptor list address register (TDLAR)
• Receive descriptor list address register (RDLAR)
• EtherC/E-DMAC status register (EESR)
• EtherC/E-DMAC status interrupt permission register (EESIPR)
• Transmit/receive status copy enable register (TRSCER)
• Receive missed-frame counter register (RMFCR)
• Transmit FIFO threshold register (TFTR)
• FIFO depth register (FDR)
• Receiving method control register (RMCR)
• E-DMAC operation control register (EDOCR)
• Receive buffer write address register (RBWAR)
• Receive descriptor fetch address register (RDFAR)
• Transmit buffer read address register (TBRAR)
• Transmit descriptor fetch address register (TDFAR)
• Flow control FIFO threshold register (FCFTR)
• Transmit interrupt register (TRIMD)
Rev. 5.00 Mar. 15, 2007 Page 266 of 794
REJ09B0237-0500