SH7619 Datasheet, PDF (321/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.2.11 FIFO Depth Register (FDR)
FDR is a 32-bit readable/writable register that specifies the depth of the transmit and receive
FIFOs.
Initial
Bit
Bit Name value R/W Description
31 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8 TFD2 to
TFD0
B'001
R/W Transmit FIFO Depth
These bits specify the depth of the transmit FIFO.
After the start of the transmission and reception, the
setting cannot be changed.
000: 256 bytes
001: 512 bytes
Other than above: Setting prohibited
7 to 3 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2 to 0
RFD2 to
RFD0
B'001
R/W Receive FIFO Depth
These bits specify the depth of the receive FIFO. After
the start of the transmission and reception, the setting
cannot be changed.
000: 256 bytes
001: 512 bytes
Other than above: Setting prohibited
Rev. 5.00 Mar. 15, 2007 Page 283 of 794
REJ09B0237-0500