SH7619 Datasheet, PDF (80/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 2 CPU
The instruction code, operation, and execution cycles of the instructions are listed in the following
tables, classified by type.
Instruction
Summary of
Instruction Code Operation
Execution
Cycles T Bit
Indicated by mnemonic. Indicated in MSB ↔ Indicates summary of
Value when no Value of T bit after
LSB order.
operation.
wait cycles are instruction is executed
inserted^*1
Explanation of
Symbols
Explanation of Symbols Explanation of Symbols Explanation of Symbols
: No change
OP.Sz SRC, DEST mmmm: Source
→, ←: Transfer direction
OP: Operation code register
Sz: Size
SRC: Source
DEST: Destination
nnnn: Destination
register
0000: R0
(xx): Memory operand
M/Q/T: Flag bits in SR
&: Logical AND of each bit
Rm: Source register
Rn: Destination
register
imm: Immediate data
disp: Displacement*²
0001: R1
.........
1111: R15
iiii: Immediate data
dddd: Displacement
|: Logical OR of each bit
^: Exclusive logical OR of
each bit
–: Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
• When there is contention between an instruction fetch and a data access
• When the destination register of a load instruction (memory → register) is also used
by the following instruction
2. Scaled (×1, ×2, or ×4) according to the instruction operand size, etc.
For details, see SH-1/SH-2/SH-DSP Software Manual.
Rev. 5.00 Mar. 15, 2007 Page 42 of 794
REJ09B0237-0500