SH7619 Datasheet, PDF (679/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(6) 100M Phase Lock Loop (PLL)
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125
MHz logic and the 100Base-Tx Transmitter.
22.6 100Base-TX Receive
CO_RX_CLK
(for MII)
MAC
(Ether C)
MII 25MHz
by 4 bits
100M
PLL
25MHz
by 4 bits
MII
4B/5B
decoder
25MHz
by 5 bits
Descrambler
and PISO
125Mbps Serial
NRZI
converter
NRZI
MLT-3
converter
DSP: Timing recovery,
equalize and BLW correction
MLT-3
MLT-3
A/D
converter
MLT-3
Magnetics
MLT-3
6 bit Data
RJ45
MLT-3
CAT-5
Shaded blocks are
part of the PHY core
Figure 22.7 Receive Data Path
The receive data path is shown in Figure 3. Detailed descriptions are given below.
(1) 100M Receive Input
The MLT-3 from the cable is fed into the Core PHY (on inputs RXP and RXM) via a 1:1 ratio
transformer. The ADC samples the incoming differential signal at a rate of 125M samples per
second. Using a 64-level quantizer it generates 6 digital bits to represent each sample. The DSP
adjusts the gain of the ADC according to the observed signal levels such that the full dynamic
range of the ADC can be used.
Rev. 5.00 Mar. 15, 2007 Page 641 of 794
REJ09B0237-0500