SH7619 Datasheet, PDF (392/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
CPU
CPU
DMAC
Burst acceptance
Non-sensitive period
DMAC
Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection
CKIO
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(High-active)
CKIO
CPU
CPU
DMAC
1st acceptance
Non-sensitive period
2nd acceptance
Acceptance
started
Bus cycle
DREQ
(Overrun 1,
high-level)
DACK
(High-active)
CPU
CPU
1st acceptance
Non-sensitive period
DMAC
2nd acceptance
DMAC
3rd acceptance
Acceptance
started
Acceptance
started
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection
Rev. 5.00 Mar. 15, 2007 Page 354 of 794
REJ09B0237-0500