SH7619 Datasheet, PDF (708/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 23 PHY Interface (PHY-IF)
Bit Bit name
Initial
value R/W Description
2
co_st_mode[2] 1
R/W PHY mode
1
co_st_mode[1] 1
Decides the initial value of the PHY mode.
0
co_st_mode[0] 0
000: 10Base-T Half Duplex. Auto-negotiation
disabled.
001: 10Base-T Full Duplex. Auto-negotiation
disabled.
010: 100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
011: 100Base-TX Full Duplex. Auto-negotiation
disabled.
CRS is active during Receive.
100: 100Base-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
101: Reserved. (Do not set this mode.)
110: Power Down mode. In this mode the PHY
wake-up in Power-Down mode (an initial value)
111: All capable. Auto-negotiation enabled.
23.2.2 PHY-IF SMI Register 2 (PHYIFSMIR2)
PHYIFSMIR2 is a 16-bit readable/writeable register, which sets the initial value of SMI register 2
in the case of the module reset the on-chip PHY module.
The changes of this register are taken by the on-chip PHY module reset with co_resetb.
PHYIFSMIR2 is initialized by power-on-reset. It is also initialized as H'0000 in the standby mode.
Bit
Bit name
Initial
value R/W Description
15 to 0 co_reg2_oui_in[15-0] All 0
R/W The initial value of SMI register 2 (= PHY
identifier 1)[15-0]
Rev. 5.00 Mar. 15, 2007 Page 670 of 794
REJ09B0237-0500