SH7619 Datasheet, PDF (441/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
In synchronous mode, clear this bit to 0.
This bit is available only in SCFCR_0 and SCFCR_1. In
SCFCR_2, this bit is reserved. The initial value is 0 and
the write value should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * The CTS signal is fixed active 0 regardless of
the input value, and the RTS signal is also
fixed 0.
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
1
RFRST
0
R/W Receive FIFO Data Register Reset
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
0
LOOP
0
R/W Loop-Back Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
Rev. 5.00 Mar. 15, 2007 Page 403 of 794
REJ09B0237-0500