SH7619 Datasheet, PDF (88/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 2 CPU
Instruction
Operation
Code
Execution
Cycles
T Bit
LDS.L @Rm+,PR
(Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 1

NOP
No operation
0000000000001001 1

RTE
Delayed branch,
0000000000101011 5

Stack area → PC/SR
SETT
1→T
0000000000011000 1
1
SLEEP
Sleep
0000000000011011 4*

STC SR,Rn
SR → Rn
0000nnnn00000010 1

STC GBR,Rn
GBR → Rn
0000nnnn00010010 1

STC VBR,Rn
VBR → Rn
0000nnnn00100010 1

STC.L SR,@–Rn
Rn–4 → Rn, SR → (Rn)
0100nnnn00000011 1

STC.L GBR,@–Rn
Rn–4 → Rn, GBR → (Rn) 0100nnnn00010011 1

STC.L VBR,@–Rn
Rn–4 → Rn, VBR → (Rn) 0100nnnn00100011 1

STS MACH,Rn
MACH → Rn
0000nnnn00001010 1

STS MACL,Rn
MACL → Rn
0000nnnn00011010 1

STS PR,Rn
PR → Rn
0000nnnn00101010 1

STS.L MACH,@–Rn
Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 1

STS.L MACL,@–Rn
Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 1

STS.L PR,@–Rn
Rn–4 → Rn, PR → (Rn)
0100nnnn00100010 1

TRAPA #imm
PC/SR → Stack area,
11000011iiiiiiii 8

(imm × 4 + VBR) → PC
Note: * Number of execution cycles until this LSI enters sleep mode.
About the number of execution cycles:
The table lists the minimum number of execution cycles. In practice, the number of
execution cycles will be increased depending on the conditions such as:
• When there is a conflict between instruction fetch and data access
• When the destination register of a load instruction (memory → register) is also used
by the instruction immediately after the load instruction.
Rev. 5.00 Mar. 15, 2007 Page 50 of 794
REJ09B0237-0500