SH7619 Datasheet, PDF (234/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
The IOIS16 signal is sampled at the falling edge of the CKIO signal in the Tpci0, Tpci0w, and
Tpci1 cycles when bits TED3 to TED0 are specified as 1.5 cycles or more, and is reflected in the
CE2 signal 1.5 cycles after the CKIO sampling point. Bits TED3 to TED0 must be specified
appropriately to satisfy the setup time of the PC card from ICIORD and ICIOWR to CEn.
Figure 7.39 shows the dynamic bus sizing basic timing.
Note that the IOIS16 signal is not supported in big endian mode. In the big endian mode, the
IOIS16 signal must be fixed low.
CKIO
A25 to A0
CExx
RD/WR
Read
Write
ICIORD
D
ICIOWR
D
BS
Tpci1
Tpci1w
Tpci1w
Tpci1w
Tpci2
Figure 7.37 Basic Timing for PCMCIA I/O Card Interface
Rev. 5.00 Mar. 15, 2007 Page 196 of 794
REJ09B0237-0500