SH7619 Datasheet, PDF (661/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
22.2 Pin Configuration
PHY module has below pins.
Table 22.1 Pin Configuration
Pin Name
Abbreviation
Analog power supply 1 Vcc1A
for PHY
Analog power supply 2 Vcc2A
for PHY
Analog power supply 3 Vcc3A
for PHY
Analog ground 1 for PHY Vss1A
Analog ground 2 for PHY Vss2A
PHY clock
CK_PHY
Differential transmit
TxP
output (+)
Differential transmit
TxM
output (-)
Differential receive input RxP
(+)
Differential receive input RxM
(-)
SPEED100 signal
SPEED100
LINK signal
CRS signal
LINK
CRS
DUPLEX signal
DUPLEX
I/O
Input
Function
Analog power supply for PHY
Input Analog power supply for PHY
Input Analog power supply for PHY
Input Analog ground for PHY
Input Analog ground for PHY
Input
For providing the external clock for PHY. Of
course you can provide a clock from internal
clock pulse generator (CPG), but you have to
pull up or down this pin in that case.
Output The differential transmit output (+) from PHY
to Ethernet network
Output The differential transmit output (-) from PHY
to Ethernet network
Input The differential receive input (+) from
Ethernet network to PHY
Input The differential receive input (-) from Ethernet
network to PHY
Output SPEED100 Output Low shows that the
operating speed is 100 Mbit/s or during Auto
negotiation
Output LINK Output (Low indicates that link is on.)
Output CRS Output (Low indicates that there is CRS
(carrier sense), keeps low after inactivation of
CRS about 128 ms.)
Output DUPLEX Output (Low indicates FULL
DUPLEX)
Rev. 5.00 Mar. 15, 2007 Page 623 of 794
REJ09B0237-0500