SH7619 Datasheet, PDF (771/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

25.4.5 Synchronous DRAM Timing
Section 25 Electrical Characteristics
CKIO
A25 to A0
A11*¹
Tr
Tc1
Tcw
t_AD1
t_AD1
Row address
Column address
t_AD1
t_AD1
t_AD1
Read A command
Td1
Tde
t_AD1
CSn
RD/WR
RAS
CAS
DQMxx
t
CSD1
t_RWD
t_RASD
t_DQMD
t_RASD
t_CASD
t_CASD
t
CSD1
t_RWD
t_DQMD
D15 to D0
BS
CKE
t_BSD
t_DACD
t_RDS2
t_RDH2
t_BSD
(High)
t_DACD
DACKn*²
Notes: * 1. Address pins connected to A10 in SDRAM
2. DACKn is the waveform when active low is selected.
Figure 25.16 Synchronous DRAM Single Read Bus Cycle (Auto-Precharge,
CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
Rev. 5.00 Mar. 15, 2007 Page 733 of 794
REJ09B0237-0500