SH7619 Datasheet, PDF (309/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.2.6 EtherC/E-DMAC Status Register (EESR)
EESR is a 32-bit readable/writable register that shows communications status information on the
E-DMAC in combination with the EtherC. The information in this register is reported in the form
of interrupts. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only bit and
not to be cleared by writing 1) and are not affected by writing 0. Each interrupt source can also be
masked by means of the corresponding bit in the EtherC/E-DMAC status interrupt permission
register (EESIPR).
The interrupts generated by this register are EINT0. For interrupt priority, see section 6.5,
Interrupt Exception Handling Vector Table.
Initial
Bit
Bit Name value R/W Description
31

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
30
TWB
0
R/W Write-Back Complete
Indicates that write-back from the E-DMAC to the
corresponding descriptor has completed. This
operation is enabled when the TIS bit in TRIMD is set
to 1.
0: Write-back has not completed, or no transmission
directive
1: Write-back has completed
29 to 27 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
26
TABT
0
R/W Transmit Abort Detection
Indicates that frame transmission by the EtherC has
been aborted because of an error during transmission.
0: Frame transmission has not been aborted or no
transmit directive
1: Frame transmit has been aborted
Rev. 5.00 Mar. 15, 2007 Page 271 of 794
REJ09B0237-0500