SH7619 Datasheet, PDF (374/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
• DMARS1
Initial
Bit
Bit Name Value R/W Description
15
C3MID5 0
14
C3MID4 0
13
C3MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 3
R/W ^(MID)
R/W ^{See table 13.2.}
12
C3MID2 0
R/W
11
C3MID1 0
R/W
10
C3MID0 0
R/W
9
C3RID1 0
8
C3RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 3
R/W ^(RID)
See table 13.2.
7
C2MID5 0
6
C2MID4 0
5
C2MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 2
R/W ^(MID)
R/W ^{See table 13.2.}
4
C2MID2 0
R/W
3
C2MID1 0
R/W
2
C2MID0 0
R/W
1
C2RID1 0
0
C2RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 2
R/W ^(RID)
See table 13.2.
Table 13.2 Transfer Request Sources
Peripheral Setting Value for One
Module
Channel (MID + RID)
MID
RID
SCIF0
H'21
001000
01
H'22
10
SCIF1
H'25
001001
01
H'26
10
SCIF2
H'29
001010
01
H'2A
10
SIOF0
H'51
010100
01
H'52
10
Function
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Rev. 5.00 Mar. 15, 2007 Page 336 of 794
REJ09B0237-0500