SH7619 Datasheet, PDF (13/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

10.3.2 Standby Control Register 2 (STBCR2)............................................................. 226
10.3.3 Standby Control Register 3 (STBCR3)............................................................. 227
10.3.4 Standby Control Register 4 (STBCR4)............................................................. 228
10.4 Sleep Mode ....................................................................................................................... 229
10.4.1 Transition to Sleep Mode.................................................................................. 229
10.4.2 Canceling Sleep Mode ...................................................................................... 229
10.5 Software Standby Mode.................................................................................................... 230
10.5.1 Transition to Software Standby Mode .............................................................. 230
10.5.2 Canceling Software Standby Mode................................................................... 231
10.6 Module Standby Mode...................................................................................................... 232
10.6.1 Transition to Module Standby Mode ................................................................ 232
10.6.2 Canceling Module Standby Function................................................................ 232
Section 11 Ethernet Controller (EtherC)..............................................................233
11.1 Features............................................................................................................................. 233
11.2 Input/Output Pins.............................................................................................................. 235
11.3 Register Description ......................................................................................................... 237
11.3.1 EtherC Mode Register (ECMR)........................................................................ 238
11.3.2 EtherC Status Register (ECSR)......................................................................... 241
11.3.3 EtherC Interrupt Permission Register (ECSIPR) .............................................. 243
11.3.4 PHY Interface Register (PIR) ........................................................................... 244
11.3.5 MAC Address High Register (MAHR)............................................................. 245
11.3.6 MAC Address Low Register (MALR).............................................................. 245
11.3.7 Receive Frame Length Register (RFLR) .......................................................... 246
11.3.8 PHY Status Register (PSR)............................................................................... 247
11.3.9 Transmit Retry Over Counter Register (TROCR) ............................................ 247
11.3.10 Delayed Collision Detect Counter Register (CDCR)........................................ 248
11.3.11 Lost Carrier Counter Register (LCCR) ............................................................. 248
11.3.12 Carrier Not Detect Counter Register (CNDCR) ............................................... 248
11.3.13 CRC Error Frame Counter Register (CEFCR).................................................. 249
11.3.14 Frame Receive Error Counter Register (FRECR)............................................. 249
11.3.15 Too-Short Frame Receive Counter Register (TSFRCR)................................... 249
11.3.16 Too-Long Frame Receive Counter Register (TLFRCR)................................... 250
11.3.17 Residual-Bit Frame Counter Register (RFCR) ................................................. 250
11.3.18 Multicast Address Frame Counter Register (MAFCR)..................................... 250
11.3.19 IPG Register (IPGR) ......................................................................................... 251
11.3.20 Automatic PAUSE Frame Set Register (APR) ................................................. 251
11.3.21 Manual PAUSE Frame Set Register (MPR) ..................................................... 252
11.3.22 PAUSE Frame Retransfer Count Set Register (TPAUSER)............................. 252
11.4 Operation .......................................................................................................................... 253
Rev. 5.00 Mar. 15, 2007 Page xiii of xxxviii