SH7619 Datasheet, PDF (206/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Setting
Setting
A3
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
A3
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
10 (16 10 (13
bits) bits)
01 (9 bits)
10 (16 10 (13
bits) bits)
10 (10 bits)
Output
Pins of Output
This Row
LSI
Address
Output
Column
Address
Pins of
SDRAM Function
Output
Pins of Output
This Row
LSI Address
Output
Column
Address
Pins of
SDRAM Function
Example of memory connection
Example of memory connection
One 256-Mbit product (4 Mwords x 16 bits x 4 banks, 9-
bit column product)
One 512-Mbit product (8 Mwords x 16 bits x 4 banks, 10-
bit column product)
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification
Burst Read: A burst read occurs in the following cases with this LSI.
1. Access size in reading is larger than data bus width.
2. 16-byte transfer in cache miss.
3. 16-byte transfer by DMAC and E-DMAC (access to non-cacheable area)
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively four times to read 16-byte consecutive data from the SDRAM
that is connected to a 32-bit data bus. The number of bursts in this access is four.
Rev. 5.00 Mar. 15, 2007 Page 168 of 794
REJ09B0237-0500