SH7619 Datasheet, PDF (779/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 25 Electrical Characteristics
CKIO
A25 to A0
A11*¹
Td1
Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Row
address
Column
address
Column Column
address address
Column
address
t_AD1
t_AD1
Read command
Tde
t_AD1
t_AD1
CSn
RD/WR
RAS
CAS
DQMxx
t_CSD1
t_RWD
t_RASD
t_RASD
t_CASD
t_DQMD
t_CSD1
t_RWD
t_CASD
t_DQMD
D15 to D0
t_BSD
BS
CKE
t_DACD
DACKn*²
t_RDS2
t_RDH2
t_BSD
(High)
t_RDS2
t_RDH2
t_DACD
Notes: * 1. Address pins connected to A10 in SDRAM
2. DACKn is the waveform when active low is selected.
Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: ACT + READ Commands, CAS Latency = 2, WTRCD = 0 Cycle)
Rev. 5.00 Mar. 15, 2007 Page 741 of 794
REJ09B0237-0500