SH7619 Datasheet, PDF (387/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
DREQ
Bus mastership returned to CPU once
Bus cycle
CPU
CPU
CPU
DMAC DMAC
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 13.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)
 Intermittent mode 16 and intermittent mode 64
In intermittent mode of cycle steal, the DMAC returns the bus mastership to other bus
master whenever a unit of transfer (byte, word, longword, or 16-byte unit) is complete. If
the next transfer request occurs after that, the DMAC gets the bus mastership from other
bus master after waiting for 16 or 64 clocks in Bφ count. The DMAC then transfers data of
one unit and returns the bus mastership to other bus master. These operations are repeated
until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus
occupation by DMA transfer than cycle-steal normal mode.
When the DMAC gets again the bus mastership, DMA transfer can be postponed in case of
entry updating due to cache miss.
This intermittent mode can be used for all transfer section; transfer request source, transfer
source, and transfer destination. The bus modes, however, must be cycle steal mode in all
channels.
Rev. 5.00 Mar. 15, 2007 Page 349 of 794
REJ09B0237-0500