SH7619 Datasheet, PDF (492/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
16.3.6 Receive Control Data Register (SIRCR)
SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR
can be specified only when the FL3 to FL0 bits in SIMDR are specified as 1xxx (x: Don't care.).
Initial
Bit
Bit Name Value R/W Description
31 to 16 SIRC0 All 0
R
15 to 0
Control Channel 0 Receive Data
Store data received from the SIOFRxD pin as control
channel 0 receive data. The position of the control
channel 0 data in the transmit or receive frame is
specified by the CD0A bit in SICDAR.
• These bits are valid only when the CD0E bit in
SICDAR is set to 1.
15 to 0 SIRC1 All 0
R
15 to 0
Control Channel 1 Receive Data
Store data received from the SIOFRxD pin as control
channel 1 receive data. The position of the control
channel 1 data in the transmit or receive frame is
specified by the CD1A bit in SICDAR.
• These bits are valid only when the CD1E bit in
SICDAR is set to 1.
Rev. 5.00 Mar. 15, 2007 Page 454 of 794
REJ09B0237-0500