SH7619 Datasheet, PDF (680/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(2) Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section
compensates for phase and amplitude distortion caused by the physical channel consisting of
magnetics, connectors, and CAT- 5 cable. The equalizer can restore the signal for any good-
quality CAT-5 cable between 1m and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low
frequency pole of the isolation transformer, then the droop characteristics of the transformer will
become significant and Baseline Wander (BLW) on the received signal will result. To prevent
corruption of the received data, the Core PHY corrects for BLW and can receive the ANSI
X3.263-1995 FDDI TP-PMD defined "killer packet" with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the
timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the
received recovered clock. This clock is used to extract the serial data from the received signal.
(3) NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3
is then converted to an NRZI data stream.
(4) Descrambling
The descrambler performs an inverse function to the scrambler in the transmitter and also
performs the Serial In Parallel Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the
incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able
to descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote PHY by searching for
IDLE symbols within a window of 4000 bytes (40us). This window ensures that a maximum
packet size of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no
interference.
If no IDLE-symbols are detected within this time-period, receive operation is aborted and the
descrambler re-starts the synchronization process.
Rev. 5.00 Mar. 15, 2007 Page 642 of 794
REJ09B0237-0500