SH7619 Datasheet, PDF (654/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 21 User Debugging Interface (H-UDI)
21.4 Operation
21.4.1 TAP Controller
Figure 21.2 shows the internal states of the TAP controller. State transitions basically conform to
the JTAG standard.
1 Test-logic-reset
0
1
0 Run-test/idle
1
Select-DR-scan
0
1
Capture-DR
0
Shift-DR 0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR-scan
0
1
Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
1
0
Figure 21.2 TAP Controller State Transitions
Note:
The transition condition is the TMS value at the rising edge of the TCK signal. The TDI
value is sampled at the rising edge of the TCK signal and is shifted at the falling edge of
the TCK signal. For details on change timing of the TDO value, see section 21.4.3, TDO
Output Timing. The TDO pin is high impedance, except in the shift-DR and shift-IR
states. A transition to the Test-Logic-Reset state is made asynchronously with TCK by
driving the TRST signal 0.
Rev. 5.00 Mar. 15, 2007 Page 616 of 794
REJ09B0237-0500