SH7619 Datasheet, PDF (383/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
Address Modes:
• Dual Address Mode
In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data
read cycle and written to the transfer destination in a data write cycle. At this time, transfer
data is temporarily stored in the DMAC. In the transfer between external memories as shown
in figure 13.5, data is read to the DMAC from one external memory in a data read cycle, and
then that data is written to the other external memory in a write cycle.
DMAC
SAR
DAR
Data buffer
Memory
Transfer source
module
Transfer destination
module
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
DMAC
First bus cycle
SAR
Memory
DAR
Transfer source
module
Data buffer
Transfer destination
module
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Figure 13.5 Data Flow of Dual Address Mode
Auto request, external request, and on-chip peripheral module request are available for the
transfer request. DACK can be output in read cycle or write cycle in dual address mode. The
channel control register (CHCR) can specify whether the DACK is output in read cycle or
write cycle.
Rev. 5.00 Mar. 15, 2007 Page 345 of 794
REJ09B0237-0500