SH7619 Datasheet, PDF (408/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 14 Compare Match Timer (CMT)
14.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has
priority over the count-up. In this case, the count-up is not performed. Figure 14.6 shows the
timing to write to CMCNT in words.
Peripheral operating
clock (Pφ)
Address
CMCSR write cycle
T1
T2
CMCNT
Internal write
CMCNT count-up
enable
CMCNT
N
M
Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT
Rev. 5.00 Mar. 15, 2007 Page 370 of 794
REJ09B0237-0500