SH7619 Datasheet, PDF (28/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Figure 16.12 Example of Receive Operation in Slave Mode ..................................................... 486
Figure 16.13 Transmit and Receive Timing (8-Bit Monaural Data (1))..................................... 490
Figure 16.14 Transmit and Receive Timing (8-Bit Monaural Data (2))..................................... 490
Figure 16.15 Transmit and Receive Timing (16-Bit Monaural Data (1))................................... 491
Figure 16.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) ........................................ 491
Figure 16.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) ........................................ 492
Figure 16.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) ........................................ 492
Figure 16.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) ........................................ 493
Figure 16.20 Transmit and Receive Timing (16-Bit Stereo Data).............................................. 493
Figure 16.21 Example of Configuration in SPI Mode ................................................................ 494
Figure 16.22 SPI Data/Clock Timing 1 (CPHA = 0).................................................................. 496
Figure 16.23 SPI Data/Clock Timing 2 (CPHA = 1).................................................................. 497
Figure 16.24 SPI Transmission/Reception Operation
(Example of Full-Duplex Transmission/Reception by the CPU with
TDMAE = 0) ........................................................................................................ 498
Figure 16.25 SPI Transmission Operation
(Example of Half-Duplex Transmission by the CPU with TDMAE = 0)............. 499
Figure 16.26 SPI Transmission Operation
(Example of Half-Duplex Transmission by DMA with TDMAE = 1) ................. 500
Figure 16.27 SPI Reception Operation
(Example of Half-Duplex Reception by DMA with RDMAE = 1)...................... 501
Section 17 Host Interface (HIF)
Figure 17.1 Block Diagram of HIF............................................................................................. 504
Figure 17.2 HIF Connection Example........................................................................................ 506
Figure 17.3 Basic Timing for HIF Interface ............................................................................... 522
Figure 17.4 HIFIDX Write and HIFGSR Read .......................................................................... 523
Figure 17.5 HIF Register Settings .............................................................................................. 523
Figure 17.6 Consecutive Data Writing to HIFRAM................................................................... 524
Figure 17.7 Consecutive Data Reading from HIFRAM ............................................................. 525
Figure 17.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0)............................................. 526
Figure 17.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)............................................. 526
Figure 17.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0) ........................................... 527
Figure 17.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1) ........................................... 527
Figure 17.12 Image of High-Impedance Control of HIF Pins by HIFEBL Pin .......................... 532
Section 19 I/O Ports
Figure 19.1 Port A ...................................................................................................................... 569
Figure 19.2 Port B ...................................................................................................................... 571
Figure 19.3 Port C ...................................................................................................................... 573
Figure 19.4 Port D ...................................................................................................................... 576
Rev. 5.00 Mar. 15, 2007 Page xxviii of xxxviii