SH7619 Datasheet, PDF (287/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 11 Ethernet Controller (EtherC)
11.3.13 CRC Error Frame Counter Register (CEFCR)
CEFCR is a 32-bit counter that indicates the number of times a frame with a CRC error was
received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter
value is cleared to 0 by a write to this register with any value.
Bit Bit Name
31 to 0 CEFC31 to
CEFC0
Initial
Value
All 0
R/W Description
R/W CRC Error Frame Count
These bits indicate the count of CRC error frames
received.
11.3.14 Frame Receive Error Counter Register (FRECR)
FRECR is a 32-bit counter that indicates the number of frames input from the PHY for which a
receive error was indicated by the RX-ER pin. FRECR is incremented each time the RX-ER pin
becomes active. When the value in this register reaches H'FFFFFFFF, the count is halted. The
counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
31 to 0 FREC31 to
FREC0
Initial
Value
All 0
R/W Description
R/W Frame Receive Error Count
These bits indicate the count of errors during frame
reception.
11.3.15 Too-Short Frame Receive Counter Register (TSFRCR)
TSFRCR is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have
been received. When the value in this register reaches H'FFFFFFFF, the count is halted. The
counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
31 to 0 TSFC31 to
TSFC0
Initial
Value
All 0
R/W Description
R/W Too-Short Frame Receive Count
These bits indicate the count of frames received with
a length of less than 64 bytes.
Rev. 5.00 Mar. 15, 2007 Page 249 of 794
REJ09B0237-0500