SH7619 Datasheet, PDF (504/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
2
BRDV2 0
R/W Baud rate generator’s Division Ratio Setting
1
BRDV1 0
0
BRDV0 0
R/W Set the frequency division ratio for the output stage of the
R/W ^{baud rate generator.}
000: Prescalar output × 1/2
001: Prescalar output × 1/4
010: Prescalar output × 1/8
011: Prescalar output × 1/16
100: Prescalar output × 1/32
101: Setting prohibited
110: Setting prohibited
111: Prescalar output × 1/1*
The final frequency division ratio of the baud rate
generator is determined by BRPS × BRDV (maximum
1/1024).
Note: *This setting is valid only when the BRPS4 to
BRPS0 bits are set to B'00000.
16.3.11 Transmit Data Assign Register (SITDAR)
SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a
frame (slot number).
Initial
Bit
Bit Name Value
15
TDLE
0
14 to 12 
All 0
R/W Description
R/W Transmit Left-Channel Data Enable
0: Disables left-channel data transmission
1: Enables left-channel data transmission
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 5.00 Mar. 15, 2007 Page 466 of 794
REJ09B0237-0500