SH7619 Datasheet, PDF (544/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
17.3 Parallel Access
17.3.1 Operation
The HIF can be accessed by combining the HIFCS, HIFRS, HIFWR, and HIFRD pins. Table 17.2
shows the correspondence between combinations of these signals and HIF operations.
Table 17.2 HIF Operations
HIFCS HIFRS
1
*
0
0
0
0
0
1
0
1
0
*
0
*
[Legend]
*: Don't care
HIFWR
*
1
0
1
0
1
0
HIFRD
*
0
1
0
1
1
0
Operation
No operation (NOP)
Read from register specified by HIFIDX[7:0]
Write to register specified by HIFIDX[7:0]
Read from status register (HIFGSR[7:0])
Write to index register (HIFIDX[7:0])
No operation (NOP)
Setting prohibited
17.3.2 Connection Method
When connecting the HIF to an external device, a method like that shown in figure 17.2 should be
used.
External device
CS
A02
WR
RD
D15 to D00
HIF
HIFCS
HIFRS
HIFWR
HIFRD
HIFD15 to HIFD00
Figure 17.2 HIF Connection Example
Rev. 5.00 Mar. 15, 2007 Page 506 of 794
REJ09B0237-0500