SH7619 Datasheet, PDF (622/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
Figure 20.1 shows a block diagram of the UBC.
Access
control
IAB LAB
Access
comparator
Address
comparator
BBRA
BARA
BAMRA
MDB
Channel A
Access
comparator
Address
comparator
BBRB
BARB
BAMRB
Data
comparator
Channel B
PC trace
Control
BBRB
BDMRB
BETR
BRSR
BRDR
BRCR
LDB/IDB
CPU state signal
[Legend]
BBRA:
BARA:
BAMRA:
BBRB:
BARB:
BAMRB:
Break bus cycle register A
Break address register A
Break address mask register A
Break bus cycle register B
Break address register B
Break address mask register B
User break request
UBC location
BDRB:
BDMRB:
BETR:
BRSR:
BRDR:
BRCR:
Break data register B
Break data mask register B
Execution times break register
Branch source register
Branch destination register
Break control register
Figure 20.1 Block Diagram of UBC
Rev. 5.00 Mar. 15, 2007 Page 584 of 794
REJ09B0237-0500